1. Field of the Invention
The present invention is generally directed to integrated circuits that require individually controllable MOS transistors.
2. Description of the Prior Art
An increased packing density as well as a shortening of the connections between components are desirable in the development of new integrated circuits. This is typically accomplished using planar silicon technology.
A diminution of the areas of MOS transistors can be achieved, for example, with a vertical, instead of a horizontal, channel course. An earlier German Letters Patent proposed a vertical MOS transistor whose source and drain regions are arranged laterally and in differing depth. The channel thereof proceeds substantially perpendicularly relative to the surface of the circuit along the sidewalls of a depression. The MOS transistor is surrounded by an insulation structure. The saving in area per transistor amounts to approximately 4F2 compared to the area of planar transistors. At approximately 16F2, however, the area of this vertical MOS transistor continues to be large.
U.S. Pat. No. 5,376,575 disclosed the employment of vertical MOS transistors for DRAM cell arrangements; i.e., memory cell arrangements having dynamic random access. Each vertical MOS transistor in the disclosed manufacturing method includes two oppositely residing sidewalls of a trench situated in a substrate. First doped regions that act as first source/drain regions of the MOS transistor are provided in the upper region of the sidewalls. Second doped regions that act as second source/drain regions are arranged under the first source/drain regions. Second source/drain regions of MOS transistors neighboring along the trench are connected to one another via a bit line. Surfaces of the sidewalls are provided with a gate oxide. A gate electrode that covers surfaces of the gate oxides lying opposite one another is provided for the MOS transistor. Shallow trenches are provided in the substrate which proceed transversely relative to bit lines, and word lines proceed transversely to the bit lines arranged therein. The word lines are laterally adjacent to gate electrodes and are thus connected thereto. Gate electrodes of MOS transistors neighboring along a word line are connected to one another via the word line. The smallest area of a memory cell obtainable with this method amounts to 6F2. What is disadvantageous about vertical MOS transistors of this type is that they can only be employed for circuit arrangements wherein the gate electrodes of the MOS transistors are connected to one another. The MOS transistors cannot be individually driven.
The present invention is directed toward an integrated circuit having MOS transistors that can be individually driven and which can occupy a relatively small area as well as a manufacturing method for such a circuit.
In an embodiment of the present invention, a first MOS transistor is adjacent to a first sidewall of a trench and a second MOS transistor is adjacent to a second sidewall of the trench lying opposite the first sidewall. The first MOS transistor and the second MOS transistor lie opposite one another. First source/drain regions of the two MOS transistors are located in the upper region of the sidewalls. A second source/drain region is divided by the two MOS transistors and is adjacent to a floor of the trench. The sidewalls of the trench are provided with a gate dielectric. The gate electrodes of the MOS transistor are arranged in the trench at the sidewalls of the trench. The gate electrodes can be individually driven via parts of a conductive layer that are arranged above the first source/drain regions.
An inventive MOS transistor can be manufactured with an area of 4F2. It is important for the manufacturing method that a conductive layer is produced before generation of the trench. The gate electrodes can be individually contacted via parts of the conductive layer.
The present invention offers the advantage that the MOS transistors can be individually driven. Such MOS transistors can thus be employed, for example, for radio-frequency circuit arrangements or for inverters. It is within the scope of the present invention to have more than two MOS transistors at a trench for manufacturing large circuit arrangements with enhanced packing density. It is also within the scope of the present invention to generate a plurality of trenches arranged parallel to each other at which MOS transistors are formed for manufacturing large circuit arrangements with enhanced packing density.
It is further within the scope of the present invention that vertical transistors of a first trench are complimentary to vertical transistors of a second trench. Also, the present invention contemplates generating a doped, well-shaped first region by implantation in which the first trench is generated and a doped, well-shaped second region in which the second trench is generated. In this case, it is advantageous to employ a first mask for the implantation of the first region that subsequently serves as mask for producing a second mask which is employed in the implantation of the second region.
It is advantageous to employ structured layers that contain silicon nitride as masks when insulating structures are produced by thermal oxidation since such masks are heat-resistant and impermeable for oxidants.
Additional features and advantages of the present invention are described in, and will be apparent from, the Detailed Description of the Preferred Embodiments and from the Drawings.